1. Field of the Invention
The present invention relates to a solid-state imaging apparatus for capturing an inputted light image.
2. Related Background Art
Imaging apparatuses using solid-state imaging devices such as charge coupled device (CCD) have been widely used in various fields such as home video. When charges of a large photodiode are to be handled, however, they may not be completely transferred by a CCD due to its low charge transfer efficiency. Therefore, of solid-state imaging apparatuses, MOS imaging sensors, which do not cause any problem in terms of charge transfer efficiency, are used in specific fields.
As the final data format of the results of imaging obtained by such an imaging sensor, a digital format is often desired. Also, in order to improve the reproduced image quality, the number of bits representing the received light intensity at the time of digital conversion should be as large as possible.
A conventional image sensor combines vertical and horizontal scanning operations so as to successively read out analog signals such as voltage level from respective pixels, while obtaining digital data each time one analog-to-digital converter performs conversion.
In order for the images captured by a large number of pixels to be processed at a high speed, it is necessary for each pixel to be subjected to a shorter time of analog-to-digital conversion. In a short time of conversion, however, it is hard to attain highly accurate digitization.
Therefore, attention has been paid to a technique in which analog-to-digital converters are provided for respective horizontal lines so that the analog-to-digital converting operation is paralleled, whereby each analog-to-digital converter can secure a sufficient time for conversion and naturally attains highly accurate digitization.
Also, in that a photosensitive section and a signal-processing section are implemented in a single tip, which is hard to realize in a CCD, the superiority of MOS image sensor has been coming to the fore.
Under these circumstances, a solid-state imaging apparatus in which analog-to-digital converters are provided for respective horizontal lines (referred to as "prior art" hereinafter") is proposed in S. L. Garverick et al., IEEE Journal of Solid-State Circuit, Vol. 30, No. 5, May 1995, pp. 533-541.
FIG. 1 is a schematic view showing the circuit configuration of the solid-state imaging apparatus in the prior art. As depicted, this apparatus comprises a photosensitive section 910 provided with N pieces of vertical photosensitive sections 911.sub.j (j=1 to N) aligned in a first direction (referred to as "horizontal direction" hereinafter). Each photosensitive section 911.sub.j comprises M pieces of photosensitive pixels 912.sub.i,j (i=1 to M) aligned in a second direction (referred to as "vertical direction" hereinafter). Each photosensitive pixel 912.sub.i,j comprises a photodiode 913 for converting an input optical signal into a current signal and a switch 914 having a first terminal connected to a signal output terminal of the photodiode 913 and a second terminal for outputting the current signal generated in the photodiode 913. The switch 914 opens and closes according to the level of received vertical scanning signal VSi. The switches 914 in the respective photosensitive pixels 912.sub.i0,j horizontally aligned at the same position (i=i0) with respect to the vertical direction simultaneously open and close according to a common vertical scanning signal VS.sub.i0, whereas the switches 914 in the respective photosensitive pixels 912.sub.i,j0 vertically aligned at the same position (j=j0) with respect to the horizontal direction open and close according to vertical scanning signals VSi different from each other. The apparatus also comprises N pieces of signal-converting circuits 915.sub.j respectively provided for the vertical photosensitive sections 911.sub.j. Each signal-converting circuits 915.sub.j outputs a digital signal DLj corresponding to the amount of charge flowing therein due to the received current signal. The apparatus further comprises an output-selecting circuit 970 for receiving the digital signals DLj outputted from the signal-converting circuits 915.sub.j and outputting the digital signal DLj outputted from the signal-converting circuit 915.sub.j designated by a horizontal scanning signal HSj; a timing control section 980 for outputting the vertical scanning signal VSi, a reset instruction signal KS, a sampling instruction signal SP, a clamping instruction signal CP, and the horizontal scanning signal HSj; and a comparison control section 990 for outputting a digital counter signal D.sub.C with a predetermined period in which the digital value carried thereby changes and comparative voltage signals +V.sub.R and -V.sub.R whose voltage levels change over a predetermined duration.
The signal-converting circuit 915.sub.j comprises an integrating circuit 920 which selectively performs a time quadrature operation of the current signal received from the vertical photosensitive section 911.sub.j and an initializing operation for the time quadrature operation and output signal so as to output a voltage signal V.sub.SO which selectively corresponds to the voltage signal of the result of time quadrature of the current signal and the initial level of voltage signal with reference to time. The integrating circuit 920 selectively performs the time quadrature operation of the current signal and the initializing operation for the time quadrature operation and output signal according to the level of the received reset instruction signal KS. The signal-converting circuit 915.sub.j also comprises a clamping circuit 930 for receiving the voltage signal V.sub.SO outputted from the integrating circuit 920 and executing a clamping operation in response to the clamping instruction signal CP; a sample-and-hold circuit 940 which receives a voltage signal V.sub.CO outputted from the clamping circuit 930, performs a sampling-and-holding operation in response to the sampling instruction signal SP, receives the comparative voltage signals +V.sub.R and -V.sub.R, and outputs a voltage signal corresponding to the sum of the levels of the voltage signal V.sub.CO and comparative voltage signal +V.sub.R and a voltage signal corresponding to the sum of the levels of the voltage signal V.sub.CO and comparative voltage signal -V.sub.R ; a comparator circuit 950 for receiving two signals outputted from the sample-and-hold circuit 940 and comparing the voltages of two signals with each other; and a latch circuit 960 which receives a comparison result signal outputted from the comparator circuit 950, receives the digital counter signal D.sub.C, and latches the value of the digital counter signal D.sub.C at a moment when the comparison result signal changes in a predetermined manner.
This apparatus reads out, as digital data, captured data of a light image formed by light incident on the photosensitive section 910 as explained in the following. FIG. 2 is a timing chart showing operations of this apparatus.
First, before executing a readout operation, the timing control section 980 sets the reset instruction signal KS to its logical true level so as to set the output of the integrating circuit 920 to a reference voltage V.sub.ref which is its initial level, while setting the clamping instruction signal CP to a logical true level so as to set the input/output voltage of the clamping circuit 930 to the reference voltage V.sub.ref which is its initial level.
Also, the comparison control section 990 outputs the comparative voltage signals +V.sub.R =V.sub.0 and -V.sub.R =-V.sub.0 (V.sub.0 &gt;0) which are initial comparative voltages.
Then, after setting the reset instruction signal KS and the clamping instruction signal CP to their logical false levels, the timing control section 980 sets a vertical scanning signal VS1, which turns on only the switch 914 of the first photosensitive pixel 912.sub.1,j in the vertical scanning operation for each vertical photosensitive section 911.sub.j, to its logical true level and outputs this signal. When the switch 914 is turned on, the charge accumulated in the photodiode 913 in response to the light received so far is outputted from the photosensitive section 910 as a current signal. Then, thus outputted current signal is accumulated by the integrating circuit 920 at its feedback capacitor and then is outputted therefrom as a voltage. The signal V.sub.SO outputted from the integrating circuit 920 is inputted into the sample-and-hold circuit 940 as the signal V.sub.CO by way of the clamping circuit 930.
The sample-and-hold circuit 940 receives the comparative voltage signals +V.sub.R and -V.sub.R and the signal V.sub.CO and outputs a sample signal S1, which is determined by the voltage level of the comparative voltage signal +V.sub.R and the voltage level of the signal V.sub.CO, and a sample signal S2, which is determined by the comparative voltage signal -V.sub.R and the voltage level of the signal V.sub.CO. Also, in cases where the sampling instruction signal SP becomes an logical false level, the sample-and-hold circuit 940 outputs the sample signals S1 and S2 at the moment when the sampling instruction signal SP has become logical false.
From the moment at which the sampling instruction signal has changed from the logical true level to the logical false level after sampling, the comparison control section 990 successively lowers the voltage level of the reference voltage signal +V.sub.R with a constant gradient, while successively increasing the voltage level of the comparative voltage signal -V.sub.R with a gradient having the same absolute value as the gradient of the comparative voltage signal +V.sub.R. As a result, the voltage level of the sample signal S1 successively decreases, while the voltage level of the sample signal S2 successively decreases.
Also, from the moment at which the sampling instruction signal SP has changed from the logical true level to the logical false level after sampling, the comparison control section 990 starts counting by means of a counter with a clock having a predetermined period and outputs the counted value as the digital counter signal D.sub.C.
The sample signals S1 and S2 outputted from the sample-and-hold circuit 940 are inputted into the comparator circuit 950, where their voltage levels are compared with each other. As mentioned earlier, the voltage of the sample signal S1 is higher than that of the sample signal S2 immediately after the shift from a sampling state to a holding state. As the voltage level of the comparative voltage signal +V.sub.R successively decreases and the voltage level of the comparative voltage signal -V.sub.R successively increases, the voltage level of the sample signal S1 coincides with that of the sample signal S2 at a certain moment. Thereafter, the voltage level of the sample signal S1 becomes lower than that of the sample signal S2. As a result, in the output of the comparator circuit 950, a comparison result signal V.sub.CM changes between before and after the moment at which the voltage level of the sample signal S1 coincides with that of the sample signal S2.
The latch circuit 960 receives the comparison result signal V.sub.CM, latches the level of the digital counter signal D.sub.C at the moment when the comparison result signal V.sub.CM changes, and outputs thus latched level.
Then, according to the setting of the horizontal scanning signal HSj, a readout operation for data concerning the first photosensitive pixels 912.sub.1,j in the vertical direction is started.
The timing control section 980 sets a horizontal scanning signal HS1, which instructs only a switch 971.sub.1 corresponding to the first photosensitive pixel 912.sub.1,1 in the horizontal direction to be selected, to its logical true level, thereby turning on only the switch 971.sub.1 corresponding to the first photosensitive pixel 912.sub.1,1.
Then, the digital signal transmitted through the switch 971.sub.1 is outputted as an output data signal V.sub.0 corresponding to the light intensity incident on the first photosensitive pixel 912.sub.1,1 in the horizontal direction.
Subsequently, the horizontal scanning signal HS1, which instructs only the switch 971.sub.1 corresponding to the first photosensitive pixel 912.sub.1,1 in the horizontal direction to be selected, is set to its logical false level, thereby terminating a readout operation for the first photosensitive pixel 912.sub.1,1 in the horizontal direction.
Then, as with the first photosensitive pixel 912.sub.1,1 in the horizontal direction, data readout operations for the second and later photosensitive pixels 912.sub.1,j in the horizontal direction are performed.
Thereafter, the timing control section 980 sets the reset instruction signal KS and camping instruction signal CP to their logical true levels, while the comparison control section 990 sets the comparative voltage signals to their initial voltage levels, thereby executing data readout operations for the second and later photosensitive pixels 912.sub.i,j in the vertical scanning operation of each vertical photosensitive section 911.sub.j.